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- {"version":3,"file":"mode-verilog-b8d8651f.js","sources":["../../node_modules/ace-builds/src-noconflict/mode-verilog.js"],"sourcesContent":["ace.define(\"ace/mode/verilog_highlight_rules\",[\"require\",\"exports\",\"module\",\"ace/lib/oop\",\"ace/mode/text_highlight_rules\"], function(require, exports, module){\"use strict\";\nvar oop = require(\"../lib/oop\");\nvar TextHighlightRules = require(\"./text_highlight_rules\").TextHighlightRules;\nvar VerilogHighlightRules = function () {\n var keywords = \"always|and|assign|automatic|begin|buf|bufif0|bufif1|case|casex|casez|cell|cmos|config|\" +\n \"deassign|default|defparam|design|disable|edge|else|end|endcase|endconfig|endfunction|endgenerate|endmodule|\" +\n \"endprimitive|endspecify|endtable|endtask|event|for|force|forever|fork|function|generate|genvar|highz0|\" +\n \"highz1|if|ifnone|incdir|include|initial|inout|input|instance|integer|join|large|liblist|library|localparam|\" +\n \"macromodule|medium|module|nand|negedge|nmos|nor|noshowcancelled|not|notif0|notif1|or|output|parameter|pmos|\" +\n \"posedge|primitive|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|rcmos|real|realtime|\" +\n \"reg|release|repeat|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|showcancelled|signed|small|specify|specparam|\" +\n \"strong0|strong1|supply0|supply1|table|task|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|\" +\n \"unsigned|use|vectored|wait|wand|weak0|weak1|while|wire|wor|xnor|xor\" +\n \"begin|bufif0|bufif1|case|casex|casez|config|else|end|endcase|endconfig|endfunction|\" +\n \"endgenerate|endmodule|endprimitive|endspecify|endtable|endtask|for|forever|function|generate|if|ifnone|\" +\n \"macromodule|module|primitive|repeat|specify|table|task|while\";\n var builtinConstants = (\"true|false|null\");\n var builtinFunctions = (\"count|min|max|avg|sum|rank|now|coalesce|main\");\n var keywordMapper = this.createKeywordMapper({\n \"support.function\": builtinFunctions,\n \"keyword\": keywords,\n \"constant.language\": builtinConstants\n }, \"identifier\", true);\n this.$rules = {\n \"start\": [{\n token: \"comment\",\n regex: \"//.*$\"\n }, {\n token: \"comment.start\",\n regex: \"/\\\\*\",\n next: [\n { token: \"comment.end\", regex: \"\\\\*/\", next: \"start\" },\n { defaultToken: \"comment\" }\n ]\n }, {\n token: \"string.start\",\n regex: '\"',\n next: [\n { token: \"constant.language.escape\", regex: /\\\\(?:[ntvfa\\\\\"]|[0-7]{1,3}|\\x[a-fA-F\\d]{1,2}|)/, consumeLineEnd: true },\n { token: \"string.end\", regex: '\"|$', next: \"start\" },\n { defaultToken: \"string\" }\n ]\n }, {\n token: \"string\",\n regex: \"'^[']'\"\n }, {\n token: \"constant.numeric\",\n regex: \"[+-]?\\\\d+(?:(?:\\\\.\\\\d*)?(?:[eE][+-]?\\\\d+)?)?\\\\b\"\n }, {\n token: keywordMapper,\n regex: \"[a-zA-Z_$][a-zA-Z0-9_$]*\\\\b\"\n }, {\n token: \"keyword.operator\",\n regex: \"\\\\+|\\\\-|\\\\/|\\\\/\\\\/|%|<@>|@>|<@|&|\\\\^|~|<|>|<=|=>|==|!=|<>|=\"\n }, {\n token: \"paren.lparen\",\n regex: \"[\\\\(]\"\n }, {\n token: \"paren.rparen\",\n regex: \"[\\\\)]\"\n }, {\n token: \"text\",\n regex: \"\\\\s+\"\n }]\n };\n this.normalizeRules();\n};\noop.inherits(VerilogHighlightRules, TextHighlightRules);\nexports.VerilogHighlightRules = VerilogHighlightRules;\n\n});\n\nace.define(\"ace/mode/verilog\",[\"require\",\"exports\",\"module\",\"ace/lib/oop\",\"ace/mode/text\",\"ace/mode/verilog_highlight_rules\",\"ace/range\"], function(require, exports, module){\"use strict\";\nvar oop = require(\"../lib/oop\");\nvar TextMode = require(\"./text\").Mode;\nvar VerilogHighlightRules = require(\"./verilog_highlight_rules\").VerilogHighlightRules;\nvar Range = require(\"../range\").Range;\nvar Mode = function () {\n this.HighlightRules = VerilogHighlightRules;\n this.$behaviour = this.$defaultBehaviour;\n};\noop.inherits(Mode, TextMode);\n(function () {\n this.lineCommentStart = \"//\";\n this.blockComment = { start: \"/*\", end: \"*/\" };\n this.$quotes = { '\"': '\"' };\n this.$id = \"ace/mode/verilog\";\n}).call(Mode.prototype);\nexports.Mode = Mode;\n\n}); (function() {\n ace.require([\"ace/mode/verilog\"], function(m) {\n if (typeof module == \"object\" && typeof exports == \"object\" && module) {\n module.exports = m;\n }\n });\n })();\n "],"names":["require","exports","module","oop","TextHighlightRules","VerilogHighlightRules","keywords","builtinConstants","builtinFunctions","keywordMapper","TextMode","Mode","m"],"mappings":"gaAAA,IAAI,OAAO,mCAAmC,CAAC,UAAU,UAAU,SAAS,cAAc,+BAA+B,EAAG,SAASA,EAASC,EAASC,EAAO,CAC9J,IAAIC,EAAMH,EAAQ,YAAY,EAC1BI,EAAqBJ,EAAQ,wBAAwB,EAAE,mBACvDK,EAAwB,UAAY,CACpC,IAAIC,EAAW,snCAYXC,EAAoB,kBACpBC,EAAoB,+CACpBC,EAAgB,KAAK,oBAAoB,CACzC,mBAAoBD,EACpB,QAAWF,EACX,oBAAqBC,CAC7B,EAAO,aAAc,EAAI,EACrB,KAAK,OAAS,CACV,MAAS,CAAC,CACF,MAAO,UACP,MAAO,OACvB,EAAe,CACC,MAAO,gBACP,MAAO,OACP,KAAM,CACF,CAAE,MAAO,cAAe,MAAO,OAAQ,KAAM,OAAS,EACtD,CAAE,aAAc,SAAW,CAC9B,CACjB,EAAe,CACC,MAAO,eACP,MAAO,IACP,KAAM,CACF,CAAE,MAAO,2BAA4B,MAAO,iDAAkD,eAAgB,EAAM,EACpH,CAAE,MAAO,aAAc,MAAO,MAAO,KAAM,OAAS,EACpD,CAAE,aAAc,QAAU,CAC7B,CACjB,EAAe,CACC,MAAO,SACP,MAAO,QACvB,EAAe,CACC,MAAO,mBACP,MAAO,iDACvB,EAAe,CACC,MAAOE,EACP,MAAO,6BACvB,EAAe,CACC,MAAO,mBACP,MAAO,6DACvB,EAAe,CACC,MAAO,eACP,MAAO,OACvB,EAAe,CACC,MAAO,eACP,MAAO,OACvB,EAAe,CACC,MAAO,OACP,MAAO,MACvB,CAAa,CACb,EACI,KAAK,eAAc,CACvB,EACAN,EAAI,SAASE,EAAuBD,CAAkB,EACtDH,EAAQ,sBAAwBI,CAEhC,CAAC,EAED,IAAI,OAAO,mBAAmB,CAAC,UAAU,UAAU,SAAS,cAAc,gBAAgB,mCAAmC,WAAW,EAAG,SAASL,EAASC,EAASC,EAAO,CAC7K,IAAIC,EAAMH,EAAQ,YAAY,EAC1BU,EAAWV,EAAQ,QAAQ,EAAE,KAC7BK,EAAwBL,EAAQ,2BAA2B,EAAE,sBACrDA,EAAQ,UAAU,EAAE,MAChC,IAAIW,EAAO,UAAY,CACnB,KAAK,eAAiBN,EACtB,KAAK,WAAa,KAAK,iBAC3B,EACAF,EAAI,SAASQ,EAAMD,CAAQ,EAC1B,UAAY,CACT,KAAK,iBAAmB,KACxB,KAAK,aAAe,CAAE,MAAO,KAAM,IAAK,MACxC,KAAK,QAAU,CAAE,IAAK,GAAG,EACzB,KAAK,IAAM,kBACf,EAAG,KAAKC,EAAK,SAAS,EACtBV,EAAQ,KAAOU,CAEf,CAAC,EAAmB,UAAW,CACX,IAAI,QAAQ,CAAC,kBAAkB,EAAG,SAASC,EAAG,CACqBV,IAC3DA,EAAA,QAAiBU,EAE7C,CAAqB,CACrB","x_google_ignoreList":[0]}
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